In a fabrication of semiconductor devices, methods frequently attempt to balance a manufacturing yield of an IC design and a density of features. Due to the resolution limitation of single patterning processes, double patterning technology is frequently used to improve a density of features in fabricated semiconductor devices. One common double patterning technology involves creating very dense grating lines and subsequently applying a cutting mask, where the dense grating lines can be created by self-aligned double patterning (SADP) or directed self assembling (DSA). Along with various design rules (e.g., contact enclosure rule), such double patterning technology can enforce a manufacturing yield level for features beyond the limitation of single patterning technology. However, such design rules are frequently overly conservative, resulting in a low density of features.
A need therefore exists for a methodology enabling a selection of design rules that allow for a high density of features of IC designs while maintaining a manufacturing yield level and for an apparatus for performing the method.